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tps54260 www.ti.com slvsa86 ? march 2010 3.5v to 60v input, 2.5a, step down converter with eco-mode ? check for samples: tps54260 1 features ? 0.8-v internal voltage reference 2 ? 3.5v to 60v input voltage range ? msop10 package with powerpad ? ? 200-m ? high-side mosfet ? supported by switcherpro ? software tool ( http://focus.ti.com/docs/toolsw/folders/print/s ? high efficiency at light loads with a pulse witcherpro.html ) skipping eco-mode ? ? for swift ? documentation, see the ti ? 138 m a operating quiescent current website at http://www.ti.com/swift ? 1.3 m a shutdown current ? 100khz to 2.5mhz switching frequency applications ? synchronizes to external clock ? 12-v, 24-v and 48-v industrial and commercial ? adjustable slow start/sequencing low power systems ? gsm, gprs modules in fleet management, ? uv and ov power good output e-meters, and security systems ? adjustable uvlo voltage and hysteresis description the tps54260 device is a 60v, 2.5a, step down regulator with an integrated high side mosfet. current mode control provides simple external compensation and flexible component selection. a low ripple pulse skip mode reduces the no load, regulated output supply current to 138 m a. using the enable pin, shutdown supply current is reduced to 1.3 m a, when the enable pin is low. under voltage lockout is internally set at 2.5v, but can be increased using the enable pin. the output voltage startup ramp is controlled by the slow start pin that can also be configured for sequencing/tracking. an open drain power good signal indicates the output is within 94% to 107% of its nominal voltage. a wide switching frequency range allows efficiency and external component size to be optimized. frequency fold back and thermal shutdown protects the part during an overload condition. the tps54260 is available in 10 pin thermally enhanced msop power pad ? package. simplified schematic efficiency vs load current 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 eco-mode, powerpad, switcherpro, swift are trademarks of texas instruments. production data information is current as of publication date. copyright ? 2010, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 0 10 20 30 40 50 60 70 80 100 0 0.5 1.0 1.5 2.0 i - output current - a o efficiency - % 2.5 3.0 90 vin=12vvout=3.3v fsw=300khz ph vin gnd boot vsense comp tps54260 en rt /clk ss /tr pwrgd
tps54260 slvsa86 ? march 2010 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. table 1. ordering information (1) t j package part number (2) ? 40 c to 150 c 10 pin msop TPS54260DGQ (1) for the most current package and ordering information see the package option addendum at the end of this document, or see the ti website at www.ti.com . (2) the dgq package is also available taped and reeled. add an r suffix to the device type (i.e., TPS54260DGQr). absolute maximum ratings (1) over operating temperature range (unless otherwise noted). value unit vin ? 0.3 to 65 en ? 0.3 to 5 boot 73 vsense ? 0.3 to 3 input voltage v comp ? 0.3 to 3 pwrgd ? 0.3 to 6 ss/tr ? 0.3 to 3 rt/clk ? 0.3 to 3.6 boot-ph 8 output voltage ph ? 0.6 to 65 v ph, 10-ns transient ? 2 to 65 voltage difference pad to gnd 200 mv en 100 m a boot 100 ma source current vsense 10 m a ph current limit a rt/clk 100 m a vin current limit a comp 100 m a sink current pwrgd 10 ma ss/tr 200 m a electrostatic discharge (hbm) qss 009-105 (jesd22-a114a) 2 kv electrostatic discharge (cdm) qss 009-147 (jesd22-c101b.01) 500 v operating junction temperature ? 40 to 150 c storage temperature ? 65 to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260
tps54260 www.ti.com slvsa86 ? march 2010 package dissipation ratings (1) thermal impedance package junction to ambient msop 57 c/w (1) test board conditions: a. 3 inches 3 inches, 2 layers, thickness: 0.062 inch b. 2-ounce copper traces located on the top and bottom of the pcb c. 6 (13 mil diameters) thermal vias located under the device package electrical characteristics t j = ? 40 c to 150 c, vin = 3.5 to 60v (unless otherwise noted) parameter test conditions min typ max unit supply voltage (vin pin) operating input voltage 3.5 60 v internal undervoltage lockout no voltage hysteresis, rising and falling 2.5 v threshold shutdown supply current en = 0 v, 25 c, 3.5 v vin 60 v 1.3 4 m a operating : nonswitching supply vsense = 0.83 v, vin = 12 v, 25 c 138 200 current enable and uvlo (en pin) enable threshold voltage no voltage hysteresis, rising and falling, 25 c 1.15 1.25 1.36 v enable threshold +50 mv ? 3.8 input current m a enable threshold ? 50 mv ? 0.9 hysteresis current ? 2.9 m a voltage reference t j = 25 c 0.792 0.8 0.808 voltage reference v 0.784 0.8 0.816 high-side mosfet vin = 3.5 v, boot-ph = 3 v 300 on-resistance m ? vin = 12 v, boot-ph = 6 v 200 410 error amplifier input current 50 na error amplifier transconductance (g m ) ? 2 m a < i comp < 2 m a, v comp = 1 v 310 m mhos ? 2 m a < i comp < 2 m a, v comp = 1 v, error amplifier transconductance (g m ) 70 m mhos during slow start v vsense = 0.4 v error amplifier dc gain v vsense = 0.8 v 10,000 v/v error amplifier bandwidth 2700 khz error amplifier source/sink v (comp) = 1 v, 100 mv overdrive 27 m a comp to switch current 10.5 a/v transconductance current limit current limit threshold vin = 12 v, t j = 25 c 3.5 6.1 a thermal shutdown thermal shutdown 182 c copyright ? 2010, texas instruments incorporated submit documentation feedback 3 product folder link(s): tps54260
tps54260 slvsa86 ? march 2010 www.ti.com electrical characteristics (continued) t j = ? 40 c to 150 c, vin = 3.5 to 60v (unless otherwise noted) parameter test conditions min typ max unit timing resistor and external clock (rt/clk pin) switching frequency range using 100 2500 khz rt mode f sw switching frequency r t = 200 k ? 450 581 720 khz switching frequency range using 300 2200 khz clk mode minimum clk input pulse width 40 ns rt/clk high threshold 1.9 2.2 v rt/clk low threshold 0.5 0.7 v rt/clk falling edge to ph rising measured at 500 khz with rt resistor in series 60 ns edge delay pll lock in time measured at 500 khz 100 m s slow start and tracking (ss/tr) charge current v ss/tr = 0.4 v 2 m a ss/tr-to-vsense matching v ss/tr = 0.4 v 45 mv ss/tr-to-reference crossover 98% nominal 1.15 v ss/tr discharge current (overload) vsense = 0 v, v(ss/tr) = 0.4 v 382 m a ss/tr discharge voltage vsense = 0 v 54 mv power good (pwrgd pin) vsense falling 92% vsense rising 94% v vsense vsense threshold vsense rising 109% vsense falling 107% hysteresis vsense falling 2% output high leakage vsense = vref, v(pwrgd) = 5.5 v, 25 c 10 na on resistance i(pwrgd) = 3 ma, vsense < 0.79 v 50 ? minimum vin for defined output v(pwrgd) < 0.5 v, ii(pwrgd) = 100 m a 0.95 1.5 v 4 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260
tps54260 www.ti.com slvsa86 ? march 2010 device information pin configuration pin functions pin i/o description name no. a bootstrap capacitor is required between boot and ph. if the voltage on this capacitor is below the boot 1 o minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. error amplifier output, and input to the output switch current comparator. connect frequency compensation comp 8 o components to this pin. enable pin, internal pull-up current source. pull below 1.2v to disable. float to enable. adjust the input en 3 i undervoltage lockout with two resistors. gnd 9 ? ground ph 10 i the source of the internal high-side power mosfet. powerpad 11 ? gnd pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. an open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or pwrgd 6 o en shut down. resistor timing and external clock. an internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. if the pin is pulled above the pll upper threshold, rt/clk 5 i a mode change occurs and the pin becomes a synchronization input. the internal amplifier is disabled and the pin is a high impedance clock input to the internal pll. if clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set function. slow-start and tracking. an external capacitor connected to this pin sets the output rise time. since the ss/tr 4 i voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. vin 2 i input supply voltage, 3.5 v to 60 v. vsense 7 i inverting node of the transconductance ( gm) error amplifier. copyright ? 2010, texas instruments incorporated submit documentation feedback 5 product folder link(s): tps54260 12 3 4 5 6 7 98 10 thermal pad (11) boot vin en ph gnd comp vsense pwrgd ss/tr rt/clk msop10 (top view)
tps54260 slvsa86 ? march 2010 www.ti.com functional block diagram 6 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 error amplifier boot charge boot uvlo uvlo current sense oscillator with pll frequency shift logic and pwm latch slope compensation pwm comparator minimum clamp pulse skip maximum clamp voltage reference overload recovery vsense ss/tr comp rt/clk ph boot vin thermal shutdown en enable comparator shutdown logic shutdown enable threshold tps54260 block diagram logic shutdown pwrgd shutdown ov gnd powerpad 7 48 5 9 11 10 1 2 3 6 uv
tps54260 www.ti.com slvsa86 ? march 2010 typical characteristics on resistance vs junction temperature voltage reference vs junction temperature figure 1. figure 2. switch current limit vs junction temperature switching frequency vs junction temperature figure 3. figure 4. switching frequency vs rt/clk resistance high switching frequency vs rt/clk resistance low frequency range frequency range figure 5. figure 6. copyright ? 2010, texas instruments incorporated submit documentation feedback 7 product folder link(s): tps54260 0 500 1000 1500 2000 2500 0 25 50 75 100 125 150 175 200 rt/clk - resistance - k w f - switching frequency - khz s v = 12 v, t = 25c i j 550 570 580 590 600 610 -50 -25 0 25 50 75 100 125 150 f - switching frequency - khz s 560 t - junction temperature - c j v = 12 v, rt = 200 k i w 0.784 0.792 0.800 0.808 0.816 -50 -25 0 25 50 75 100 125 150 v - voltage reference - v ref t - junction temperature - c j v = 12 v i 0 100 200 300 400 500 200 300 400 500 600 700 800 900 1000 1100 rt/clk - resistance - k w f - switching frequency - khz s 1200 v = 12 v, t = 25c i j 5.0 5.5 6.0 7.0 -50 -25 0 25 50 75 100 125 150 switch current - a t - junction temperature - c j 6.5 v = 12 v i 0 125 250 375 500 -50 -25 0 25 50 75 100 125 150 t - junction temperature - c j rdson - static drain-source on-state resistance - m w boot-ph = 3 v boot-ph = 6 v v = 12 v i
tps54260 slvsa86 ? march 2010 www.ti.com typical characteristics (continued) ea transconductance during slow start vs junction temperature ea transconductance vs junction temperature figure 7. figure 8. en pin voltage vs junction temperature en pin current vs junction temperature figure 9. figure 10. en pin current vs junction temperature ss/tr charge current vs junction temperature figure 11. figure 12. 8 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 -3 -2.5 -2 -1.5 -1 -50 -25 0 25 50 75 100 125 150 i - a (ss/tr) m t - junction temperature - c j v = 12 v i 20 60 100 120 -50 -25 0 25 50 75 100 125 150 gm - a/v m t - junction temperature - c j v = 12 v i 40 80 -1 -0.95 -0.9 -0.85 -0.8 -50 -25 0 25 50 75 100 125 150 i - a (en) m t - junction temperature - c j v = 12 v, v = threshold -50 mv i i(en) 200 250 300 350 400 500 -50 -25 0 25 50 75 100 125 150 gm - a/v m t - junction temperature - c j v = 12 v i 450 -4.25 -4 -3.75 -3.5 -3.25 -50 -25 0 25 50 75 100 125 150 i - a (en) m t - junction temperature - c j v = 12 v, v = threshold +50 mv i i(en) 1.10 1.20 1.30 1.40 -50 -25 0 25 50 75 100 125 150 en - threshold - v t - junction temperature - c j v = 12 v i
tps54260 www.ti.com slvsa86 ? march 2010 typical characteristics (continued) ss/tr discharge current vs junction temperature switching frequency vs vsense figure 13. figure 14. shutdown supply current vs junction temperature shutdown supply current vs input voltage (v in ) figure 15. figure 16. vin supply current vs junction temperature vin supply current vs input voltage figure 17. figure 18. copyright ? 2010, texas instruments incorporated submit documentation feedback 9 product folder link(s): tps54260 0 0.5 1 1.5 2 0 10 20 30 40 50 60 v - input voltage - v i i - a (vin) m t = 25c j 70 110 130 150 170 210 -50 0 50 100 150 i - a (vin) m t - junction temperature - c j v = 12 v, v = 0.83 v i i(vsense) 90 190 0 20 40 60 80 100 0 0.2 0.4 0.6 0.8 v - v sense v = 12 v, t = 25c i j % of nominal f sw 200 275 350 425 575 -50 0 50 100 150 i - a i(ss/tr) m t - junction temperature - c j v = 12 v i 500 110 130 150 170 0 20 40 60 i - a (vin) m v - input voltage - v i t = 25 c, v = 0.83 v j i(vsense) o 0 0.5 1 1.5 2 -50 -25 0 25 50 75 100 125 150 i - a (vin) m t - junction temperature - c j v = 12 v i
tps54260 slvsa86 ? march 2010 www.ti.com typical characteristics (continued) pwrgd on resistance vs junction temperature pwrgd threshold vs junction temperature figure 19. figure 20. boot-ph uvlo vs junction temperature input voltage (uvlo) vs junction temperature figure 21. figure 22. ss/tr to vsense offset vs vsense ss/tr to vsense offset vs temperature figure 23. figure 24. 10 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 0 100 200 300 400 500 0 100 200 300 400 500 600 700 800 vsense - mv offset - mv 600 v = 12 v, i t = 25 c j o 1.5 1.8 2 2.3 2.5 -50 -25 0 25 50 75 100 125 150 v - v i(boot-ph) t - junction temperature - c j 2 2.25 2.50 2.75 3 -50 -25 0 25 50 75 100 125 150 v - v i(vin) t - junction temperature - c j 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 150 rdson - w t - junction temperature - c j v = 12 v i 85 90 95 100 105 110 115 -50 -25 0 25 50 75 100 125 150 pwrgd threshold - % of v ref vsense falling vsense rising vsense falling vsense rising v = 12 v i t - junction temperature - c j 0 10 20 30 40 50 60 -50 -25 0 25 50 75 100 125 150 offset - mv t - junction temperature - c j v = 0.4 v (ss/tr) v = 12 v i
tps54260 www.ti.com slvsa86 ? march 2010 overview the tps54260 device is a 60-v, 2.5-a, step-down (buck) regulator with an integrated high side n-channel mosfet. to improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. the wide switching frequency of 100khz to 2500khz allows for efficiency and size optimization when selecting the output filter components. the switching frequency is adjusted using a resistor to ground on the rt/clk pin. the device has an internal phase lock loop (pll) on the rt/clk pin that is used to synchronize the power switch turn on to a falling edge of an external system clock. the tps54260 has a default start up voltage of approximately 2.5v. the en pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (uvlo) threshold with two external resistors. in addition, the pull up current provides a default condition. when the en pin is floating the device will operate. the operating current is 138 m a when not switching and under no load. when the device is disabled, the supply current is 1.3 m a. the integrated 200m ? high side mosfet allows for high efficiency power supply designs capable of delivering 2.5 amperes of continuous current to a load. the tps54260 reduces the external component count by integrating the boot recharge diode. the bias voltage for the integrated high side mosfet is supplied by a capacitor on the boot to ph pin. the boot capacitor voltage is monitored by an uvlo circuit and will turn the high side mosfet off when the boot voltage falls below a preset threshold. the tps54260 can operate at high duty cycles because of the boot uvlo. the output voltage can be stepped down to as low as the 0.8v reference. the tps54260 has a power good comparator (pwrgd) which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. the pwrgd pin is an open drain output which deasserts when the vsense pin voltage is between 94% and 107% of the nominal output voltage allowing the pin to transition high when a pull-up resistor is used. the tps54260 minimizes excessive output overvoltage (ov) transients by taking advantage of the ov power good comparator. when the ov comparator is activated, the high side mosfet is turned off and masked from turning on until the output voltage is lower than 107%. the ss/tr (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. a small value capacitor should be coupled to the pin to adjust the slow start time. a resistor divider can be coupled to the pin for critical power supply sequencing requirements. the ss/tr pin is discharged before the output powers up. this discharging ensures a repeatable restart after an over-temperature fault, uvlo fault or a disabled condition. the tps54260, also, discharges the slow start capacitor during overload conditions with an overload recovery circuit. the overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. a frequency foldback circuit reduces the switching frequency during startup and overcurrent fault conditions to help control the inductor current. copyright ? 2010, texas instruments incorporated submit documentation feedback 11 product folder link(s): tps54260
tps54260 slvsa86 ? march 2010 www.ti.com detailed description fixed frequency pwm control the tps54260 uses an adjustable fixed frequency, peak current mode control. the output voltage is compared through external resistors on the vsense pin to an internal voltage reference by an error amplifier which drives the comp pin. an internal oscillator initiates the turn on of the high side power switch. the error amplifier output is compared to the high side power switch current. when the power switch current reaches the level set by the comp voltage, the power switch is turned off. the comp pin voltage will increase and decrease as the output current increases and decreases. the device implements a current limit by clamping the comp pin voltage to a maximum level. the eco-mode ? is implemented with a minimum clamp on the comp pin. slope compensation output current the tps54260 adds a compensating ramp to the switch current signal. this slope compensation prevents sub-harmonic oscillations. the available peak inductor current remains constant over the full duty cycle range. pulse skip eco-mode the tps54260 operates in a pulse skip eco mode at light load currents to improve efficiency by reducing switching and gate drive losses. the tps54260 is designed so that if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the device enters eco mode. this current threshold is the current level corresponding to a nominal comp voltage or 500mv. when in eco-mode, the comp pin voltage is clamped at 500mv and the high side mosfet is inhibited. further decreases in load current or in output voltage can not drive the comp pin below this clamp voltage level. since the device is not switching, the output voltage begins to decay. as the voltage control loop compensates for the falling output voltage, the comp pin voltage begins to rise. at this time, the high side mosfet is enabled and a switching pulse initiates on the next switching cycle. the peak current is set by the comp pin voltage. the output voltage re-charges the regulated value, then the peak switch current starts to decrease, and eventually falls below the eco mode threshold at which time the device again enters eco mode. for eco mode operation, the tps54260 senses peak current, not average or load current, so the load current where the device enters eco mode is dependent on the output inductor value. for example, the circuit in figure 49 enters eco mode at about 5 ma of output current. when the load current is low and the output voltage is within regulation, the device enters a sleep mode and draws only 138 m a input quiescent current. the internal pll remains operating when in sleep mode. when operating at light load currents in the pulse skip mode, the switching transitions occur synchronously with the external clock signal. low dropout operation and bootstrap voltage (boot) the tps54260 has an integrated boot regulator, and requires a small ceramic capacitor between the boot and ph pins to provide the gate drive voltage for the high side mosfet. the boot capacitor is refreshed when the high side mosfet is off and the low side diode conducts. the value of this ceramic capacitor should be 0.1 m f. a ceramic capacitor with an x7r or x5r grade dielectric with a voltage rating of 10v or higher is recommended because of the stable characteristics overtemperature and voltage. to improve drop out, the tps54260 is designed to operate at 100% duty cycle as long as the boot to ph pin voltage is greater than 2.1v. when the voltage from boot to ph drops below 2.1v, the high side mosfet is turned off using an uvlo circuit which allows the low side diode to conduct and refresh the charge on the boot capacitor. since the supply current sourced from the boot capacitor is low, the high side mosfet can remain on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the switching regulator is high. the effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the power mosfet, inductor resistance, low side diode and printed circuit board resistance. during operating conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the high side mosfet can remain on for 100% of the duty cycle to maintain output regulation, until the boot to ph voltage falls below 2.1v. 12 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260
tps54260 www.ti.com slvsa86 ? march 2010 detailed description (continued) attention must be taken in maximum duty cycle applications which experience extended time periods with light loads or no load. when the voltage across the boot capacitor falls below the 2.1v uvlo threshold, the high side mosfet is turned off, but there may not be enough inductor current to pull the ph pin down to recharge the boot capacitor. the high side mosfet of the regulator stops switching because the voltage across the boot capacitor is less than 2.1v. the output capacitor then decays until the difference in the input voltage and output voltage is greater than 2.1v, at which point the boot uvlo threshold is exceeded, and the device starts switching again until the desired output voltage is reached. this operating condition persists until the input voltage and/or the load current increases. it is recommended to adjust the vin stop voltage greater than the boot uvlo trigger condition at the minimum load of the application using the adjustable vin uvlo feature with resistors on the en pin. the start and stop voltages for typical 3.3v and 5v output applications are shown in figure 25 and figure 26 . the voltages are plotted versus load current. the start voltage is defined as the input voltage needed to regulate the output within 1%. the stop voltage is defined as the input voltage at which the output drops by 5% or stops switching. during high duty cycle conditions, the inductor current ripple increases while the boot capacitor is being recharged resulting in an increase in ripple voltage on the output. this is due to the recharge time of the boot capacitor being longer than the typical high side off time when switching occurs every cycle. figure 25. 3.3v start/stop voltage figure 26. 5.0v start/stop voltage error amplifier the tps54260 has a transconductance amplifier for the error amplifier. the error amplifier compares the vsense voltage to the lower of the ss/tr pin voltage or the internal 0.8v voltage reference. the transconductance (gm) of the error amplifier is 310 m a/v during normal operation. during the slow start operation, the transconductance is a fraction of the normal operating gm. when the voltage of the vsense pin is below 0.8v and the device is regulating using the ss/tr voltage, the gm is 70 m a/v. the frequency compensation components (capacitor, series resistor and capacitor) are added to the comp pin to ground. voltage reference the voltage reference system produces a precise 2% voltage reference over temperature by scaling the output of a temperature stable bandgap circuit. adjusting the output voltage the output voltage is set with a resistor divider from the output node to the vsense pin. it is recommended to use 1% tolerance or better divider resistors. start with a 10 k ? for the r2 resistor and use the equation 1 to calculate r1. to improve efficiency at light loads consider using larger value resistors. if the values are too high the regulator will be more susceptible to noise and voltage errors from the vsense input current will be noticeable copyright ? 2010, texas instruments incorporated submit documentation feedback 13 product folder link(s): tps54260 3 3.2 3.4 3.6 3.8 4 0 0.05 0.10 0.15 0.20 i - output current - a o v - input voltage - v i v = 3.3 v o start stop 4.6 4.8 5 5.2 5.4 5.6 0 0.05 0.10 0.15 0.20 i - output current - a o v - input voltage - v i v = 5 v o start stop
tps54260 slvsa86 ? march 2010 www.ti.com detailed description (continued) (1) enable and adjusting undervoltage lockout the tps54260 is disabled when the vin pin voltage falls below 2.5 v. if an application requires a higher undervoltage lockout (uvlo), use the en pin as shown in figure 27 to adjust the input voltage uvlo by using the two external resistors. though it is not necessary to use the uvlo adjust registers, for operation it is highly recommended to provide consistent power up behavior. the en pin has an internal pull-up current source, i1, of 0.9 m a that provides the default condition of the tps54260 operating when the en pin floats. once the en pin voltage exceeds 1.25v, an additional 2.9 m a of hysteresis, ihys, is added. this additional current facilitates input voltage hysteresis. use equation 2 to set the external hysteresis for the input voltage. use equation 3 to set the input start voltage. figure 27. adjustable undervoltage lockout (uvlo) (2) (3) another technique to add input voltage hysteresis is shown in figure 28 . this method may be used, if the resistance values are high from the previous method and a wider voltage hysteresis is needed. the resistor r3 sources additional hysteresis current into the en pin. figure 28. adding additional hysteresis 14 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 en ihys vin + - tps54260 r 1 r 2 vout r3 i1 0.9 a m 2.9 a m 1.25 v start stop hys v v r1 i - = vout 0.8v r1 = r2 0.8 v - ? ? ? ? en vin + - tps54260 r 1 r 2 ihys i1 0.9 a m 1.25 v 2.9 a m ena start ena 1 v r2 v v i r1 = - +
tps54260 www.ti.com slvsa86 ? march 2010 detailed description (continued) (4) (5) copyright ? 2010, texas instruments incorporated submit documentation feedback 15 product folder link(s): tps54260 ena start ena ena 1 v r2 v v v i r1 r3 = - + - start stop out hys v v r1 v i r3 - = +
tps54260 slvsa86 ? march 2010 www.ti.com detailed description (continued) slow start/tracking pin (ss/tr) the tps54260 effectively uses the lower voltage of the internal voltage reference or the ss/tr pin voltage as the power-supply's reference voltage and regulates the output accordingly. a capacitor on the ss/tr pin to ground implements a slow start time. the tps54260 has an internal pull-up current source of 2 m a that charges the external slow start capacitor. the calculations for the slow start time (10% to 90%) are shown in equation 6 . the voltage reference (v ref ) is 0.8 v and the slow start current (i ss ) is 2 m a. the slow start capacitor should remain lower than 0.47 m f and greater than 0.47nf. (6) at power up, the tps54260 will not start switching until the slow start pin is discharged to less than 40 mv to ensure a proper power up, see figure 29 . also, during normal operation, the tps54260 will stop switching and the ss/tr must be discharged to 40 mv, when the vin uvlo is exceeded, en pin pulled below 1.25v, or a thermal shutdown event occurs. the vsense voltage will follow the ss/tr pin voltage with a 45mv offset up to 85% of the internal voltage reference. when the ss/tr voltage is greater than 85% on the internal reference voltage the offset increases as the effective system reference transitions from the ss/tr voltage to the internal voltage reference (see figure 23 ). the ss/tr voltage will ramp linearly until clamped at 1.7v. figure 29. operation of ss/tr pin when starting overload recovery circuit the tps54260 has an overload recovery (olr) circuit. the olr circuit will slow start the output from the overload voltage to the nominal regulation voltage once the fault condition is removed. the olr circuit will discharge the ss/tr pin to a voltage slightly greater than the vsense pin voltage using an internal pull down of 382 m a when the error amplifier is changed to a high voltage from a fault condition. when the fault condition is removed, the output will slow start from the fault voltage to nominal output voltage. 16 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 en ss/tr v sense vout tss(ms) iss( a) css(nf) = vref (v) 0.8 m
tps54260 www.ti.com slvsa86 ? march 2010 detailed description (continued) sequencing many of the common power supply sequencing methods can be implemented using the ss/tr, en and pwrgd pins. the sequential method can be implemented using an open drain output of a power on reset pin of another device. the sequential method is illustrated in figure 30 using two tps54260 devices. the power good is coupled to the en pin on the tps54260 which will enable the second power supply once the primary supply reaches regulation. if needed, a 1nf ceramic capacitor on the en pin of the second power supply will provide a 1ms start up delay. figure 31 shows the results of figure 30 . figure 30. schematic for sequential start-up figure 31. sequential startup using en and sequence pwrgd figure 32. schematic for ratiometric start-up figure 33. ratio-metric startup using coupled sequence ss/tr pins copyright ? 2010, texas instruments incorporated submit documentation feedback 17 product folder link(s): tps54260 en1 pwrgd1 vout1 vout2 ss /tr tps54260 en pwrgd ss /tr en pwrgd en1, en2 vout1 vout2 en tps54160 3 ss/tr 4 pwrgd 6 en tps54160 3 ss/tr 4 pwrgd 6 tps54260 tps54260
tps54260 slvsa86 ? march 2010 www.ti.com detailed description (continued) figure 32 shows a method for ratio-metric start up sequence by connecting the ss/tr pins together. the regulator outputs will ramp up and reach regulation at the same time. when calculating the slow start time the pull up current source must be doubled in equation 6 . figure 33 shows the results of figure 32 . figure 34. schematic for ratiometric and simultaneous start-up sequence ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of r1 and r2 shown in figure 34 to the output of the power supply that needs to be tracked or another voltage reference source. using equation 7 and equation 8 , the tracking resistors can be calculated to initiate the vout2 slightly before, after or at the same time as vout1. equation 9 is the voltage difference between vout1 and vout2 at the 95% of nominal output regulation. the deltav variable is zero volts for simultaneous sequencing. to minimize the effect of the inherent ss/tr to vsense offset (vssoffset) in the slow start circuit and the offset created by the pullup current source (iss) and tracking resistors, the vssoffset and iss are included as variables in the equations. to design a ratio-metric start up in which the vout2 voltage is slightly greater than the vout1 voltage when vout2 reaches regulation, use a negative number in equation 7 through equation 9 for deltav. equation 9 will result in a positive number for applications which the vout2 is slightly lower than vout1 when vout2 regulation is achieved. since the ss/tr pin must be pulled below 40mv before starting after an en, uvlo or thermal shutdown fault, careful selection of the tracking resistors is needed to ensure the device will restart after a fault. make sure the calculated r1 value from equation 7 is greater than the value calculated in equation 10 to ensure the device can recover from a fault. as the ss/tr voltage becomes more than 85% of the nominal reference voltage the vssoffset becomes larger as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. the ss/tr pin voltage needs to be greater than 1.3v for a complete handoff to the internal voltage reference as shown in figure 23 . (7) 18 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 vout2 + deltav vssoffset r1 = vref iss ss/tr tps54260 en pwrgd ss/ tr en pwrgd vout 1 vout 2 r 1 r 2 r3 r 4 tps54260
tps54260 www.ti.com slvsa86 ? march 2010 detailed description (continued) (8) (9) (10) figure 35. ratio-metric startup with tracking figure 36. ratiometric startup with tracking resistors resistors figure 37. simultaneous startup with tracking resistor copyright ? 2010, texas instruments incorporated submit documentation feedback 19 product folder link(s): tps54260 r1 > 2800 vout1 180 deltav - en vout1 vout2 vref r1 r2 = vout2 + deltav vref - en vout1 vout2 deltav = vout1 vout2 - en vout1 vout2
tps54260 slvsa86 ? march 2010 www.ti.com detailed description (continued) constant switching frequency and timing resistor (rt/clk pin) the switching frequency of the tps54260 is adjustable over a wide range from approximately 100khz to 2500khz by placing a resistor on the rt/clk pin. the rt/clk pin voltage is typically 0.5v and must have a resistor to ground to set the switching frequency. to determine the timing resistance for a given switching frequency, use equation 11 or the curves in figure 38 or figure 39 . to reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should be considered. the minimum controllable on time is typically 135ns and limits the maximum operating input voltage. the maximum switching frequency is also limited by the frequency shift circuit. more discussion on the details of the maximum switching frequency is located below. (11) switching frequency switching frequency vs vs rt/clk resistance high frequency range rt/clk resistance low frequency range figure 38. high range rt figure 39. low range rt overcurrent protection and frequency shift the tps54260 implements current mode control which uses the comp pin voltage to turn off the high side mosfet on a cycle by cycle basis. each cycle the switch current and comp pin voltage are compared, when the peak switch current intersects the comp voltage, the high side switch is turned off. during overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the comp pin high, increasing the switch current. the error amplifier output is clamped internally, which functions as a switch current limit. to increase the maximum operating switching frequency at high input voltages the tps54260 implements a frequency shift. the switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on vsense pin. the device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. since the device can only divide the switching frequency by 8, there is a maximum input voltage limit in which the device operates and still have frequency shift protection. during short-circuit events (particularly with high input voltage applications), the control loop has a finite minimum controllable on time and the output has a low voltage. during the switch on time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on time. during the switch off time, the inductor would normally not have enough off time and output voltage for the inductor to ramp down by the ramp up amount. the frequency shift effectively increases the off time allowing the current to ramp down. 20 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 0 100 200 300 400 500 200 300 400 500 600 700 800 900 1000 1100 rt/clk - resistance - k w f - switching frequency - khz s 1200 v = 12 v, t = 25c i j 0 500 1000 1500 2000 2500 0 25 50 75 100 125 150 175 200 f - switching frequency - khz s rt/clk - clock resistance - k w v = 12 v, t = 25c i j rt kohm sw khz 1.0888 206033 ( ) = | ( )
tps54260 www.ti.com slvsa86 ? march 2010 detailed description (continued) selecting the switching frequency the switching frequency that is selected should be the lower value of the two equations, equation 12 and equation 13 . equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. setting the switching frequency above this value will cause the regulator to skip switching pulses. equation 13 is the maximum switching frequency limit set by the frequency shift protection. to have adequate output short circuit protection at high input voltages, the switching frequency should be set to be less than the fsw(maxshift) frequency. in equation 13 , to calculate the maximum switching frequency one must take into account that the output voltage decreases from the nominal voltage to 0 volts, the fdiv integer increases from 1 to 8 corresponding to the frequency shift. in figure 40 , the solid line illustrates a typical safe operating area regarding frequency shift and assumes the output voltage is zero volts, and the resistance of the inductor is 0.130 ? , fet on resistance of 0.2 ? and the diode voltage drop is 0.5v. the dashed line is the maximum switching frequency to avoid pulse skipping. enter these equations in a spreadsheet or other software or use the switcherpro design software to determine the switching frequency. (12) (13) i l inductor current rdc inductor resistance v in maximum input voltage v out output voltage v outsc output voltage during short vd diode voltage drop r ds(on) switch on resistance t on controllable on time ? div frequency divide equals (1, 2, 4, or 8) figure 40. maximum switching frequency vs. input voltage copyright ? 2010, texas instruments incorporated submit documentation feedback 21 product folder link(s): tps54260 ( ) ( ) l outsc sw shift on in l (i rdc v vd) div t v i x rhs vd ? ? + + = ? ? - + ? f f skip shift 10 20 30 40 50 60 25002000 1500 1000 500 0 f - switching frequency - khz s v - input voltage - v i v = 3.3 v o ( ) ( ) ( ) l out sw max skip on in l i rdc v vd 1 t v i rhs vd ? ? + + ? ? = ? ? ? - + ? ? f
tps54260 slvsa86 ? march 2010 www.ti.com detailed description (continued) how to interface to rt/clk pin the rt/clk pin can be used to synchronize the regulator to an external system clock. to implement the synchronization feature connect a square wave to the rt/clk pin through the circuit network shown in figure 41 . the square wave amplitude must transition lower than 0.5v and higher than 2.2v on the rt/clk pin and have an on time greater than 40 ns and an off time greater than 40 ns. the synchronization frequency range is 300 khz to 2200 khz. the rising edge of the ph will be synchronized to the falling edge of rt/clk pin signal. the external synchronization circuit should be designed in such a way that the device will have the default frequency set resistor connected from the rt/clk pin to ground should the synchronization signal turn off. it is recommended to use a frequency set resistor connected as shown in figure 41 through a 50 ? resistor to ground. the resistor should set the switching frequency close to the external clk frequency. it is recommended to ac couple the synchronization signal through a 10 pf ceramic capacitor to rt/clk pin and a 4k ? series resistor. the series resistor reduces ph jitter in heavy load applications when synchronizing to an external clock and in applications which transition from synchronizing to rt mode. the first time the clk is pulled above the clk threshold the device switches from the rt resistor frequency to pll mode. the internal 0.5v voltage source is removed and the clk pin becomes high impedance as the pll starts to lock onto the external signal. since there is a pll on the regulator the switching frequency can be higher or lower than the frequency set with the external resistor. the device transitions from the resistor mode to the pll mode and then will increase or decrease the switching frequency until the pll locks onto the clk frequency within 100 microseconds. when the device transitions from the pll to resistor mode the switching frequency will slow down from the clk frequency to 150 khz, then reapply the 0.5v voltage and the resistor will then set the switching frequency. the switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on vsense pin. the device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. figure 42 , figure 43 and figure 44 show the device synchronized to an external system clock in continuous conduction mode (ccm) discontinuous conduction (dcm) and pulse skip mode (psm). figure 41. synchronizing to a system clock 22 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 rt/clk tps54260 clock source pll r fset 10 pf 4 k w 50 w ext
tps54260 www.ti.com slvsa86 ? march 2010 detailed description (continued) figure 42. plot of synchronizing in ccm figure 43. plot of synchronizing in dcm figure 44. plot of synchronizing in psm power good (pwrgd pin) the pwrgd pin is an open drain output. once the vsense pin is between 94% and 107% of the internal voltage reference the pwrgd pin is de-asserted and the pin floats. it is recommended to use a pull-up resistor between the values of 10 and 100k ? to a voltage source that is 5.5v or less. the pwrgd is in a defined state once the vin input voltage is greater than 1.5v but with reduced current sinking capability. the pwrgd will achieve full current sinking capability as vin input voltage approaches 3v. copyright ? 2010, texas instruments incorporated submit documentation feedback 23 product folder link(s): tps54260 il ext ph ext il ph ext il ph
tps54260 slvsa86 ? march 2010 www.ti.com detailed description (continued) the pwrgd pin is pulled low when the vsense is lower than 92% or greater than 109% of the nominal internal reference voltage. also, the pwrgd is pulled low, if the uvlo or thermal shutdown are asserted or the en pin pulled low. overvoltage transient protection the tps54260 incorporates an overvoltage transient protection (ovtp) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low value output capacitance. for example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. if the vsense pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error amplifier output to a high voltage. thus, requesting the maximum output current. once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state duty cycle. in some applications, the power supply output voltage can respond faster than the error amplifier output can respond, this actuality leads to the possibility of an output overshoot. the ovtp feature minimizes the output overshoot, when using a low value output capacitor, by implementing a circuit to compare the vsense pin voltage to ovtp threshold which is 109% of the internal voltage reference. if the vsense pin voltage is greater than the ovtp threshold, the high side mosfet is disabled preventing current from flowing to the output and minimizing output overshoot. when the vsense voltage drops lower than the ovtp threshold, the high side mosfet is allowed to turn on at the next clock cycle. thermal shutdown the device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182 c. the thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. once the die temperature decreases below 182 c, the device reinitiates the power up sequence by discharging the ss/tr pin. small signal model for loop response figure 45 shows an equivalent model for the tps54260 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. the error amplifier is a transconductance amplifier with a gm ea of 310 m a/v. the error amplifier can be modeled using an ideal voltage controlled current source. the resistor r o and capacitor c o model the open loop gain and frequency response of the amplifier. the 1mv ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. plotting c/a shows the small signal response of the frequency compensation. plotting a/b shows the small signal response of the overall loop. the dynamic loop response can be checked by replacing r l with a current source with the appropriate load step amplitude and step rate in a time domain analysis. this equivalent model is only valid for continuous conduction mode designs. 24 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260
tps54260 www.ti.com slvsa86 ? march 2010 detailed description (continued) figure 45. small signal model for loop response simple small signal model for peak current mode control figure 46 describes a simple small signal model that can be used to understand how to design the frequency compensation. the tps54260 power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. the control to output transfer function is shown in equation 14 and consists of a dc gain, one dominant pole, and one esr zero. the quotient of the change in switch current and the change in comp pin voltage (node c in figure 45 ) is the power stage transconductance. the gm ps for the tps54260 is 10.5 a/v. the low-frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in equation 15 . as the load current increases and decreases, the low-frequency gain decreases and increases, respectively. this variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see equation 16 ). the combined effect is highlighted by the dashed line in the right half of figure 46 . as the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-db crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. the type of output capacitor chosen determines whether the esr zero has a profound effect on the frequency compensation design. using high esr aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin increases from the esr zero at the lower frequencies (see equation 17 ). copyright ? 2010, texas instruments incorporated submit documentation feedback 25 product folder link(s): tps54260 vsense comp v o r1 r3 c1 c2 r2 co ro gm ea 310 a/v m 0.8 v power stage gm 10.5 a/v ps ph r esr c out r l b a c
tps54260 slvsa86 ? march 2010 www.ti.com detailed description (continued) figure 46. simple small signal model and frequency response for peak current mode control (14) (15) (16) (17) small signal model for frequency compensation the tps54260 uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits. compensation circuits type 2a, type 2b, and type 1 are shown in figure 47 . type 2 circuits most likely implemented in high bandwidth power-supply designs using low esr output capacitors. the type 1 circuit is used with power-supply designs with high-esr aluminum electrolytic or tantalum capacitors.. equation 18 and equation 19 show how to relate the frequency response of the amplifier to the small signal model in figure 47 . the open-loop gain and bandwidth are modeled using the r o and c o shown in figure 47 . see the application section for a design example using a type 2a network with a low esr output capacitor. equation 18 through equation 27 are provided as a reference for those who prefer to compensate using the preferred methods. those who prefer to use prescribed method use the method outlined in the application section or use switched information. 26 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 z out esr 1 c r 2 = p f v o r esr c out r l vc gm ps fp fz adc ps l adc = gm r p out l 1 f c r 2 = p z out c p s 1 2 v adc v s 1 2 ? ? + ? p ? = ? ? + ? p ? f f
tps54260 www.ti.com slvsa86 ? march 2010 detailed description (continued) figure 47. types of frequency compensation figure 48. frequency response of the type 2a and type 2b frequency compensation (18) (19) (20) (21) (22) (23) copyright ? 2010, texas instruments incorporated submit documentation feedback 27 product folder link(s): tps54260 f f f z1 p1 p2 s 1 2 ea a0 s s 1 1 2 2 ? ? + ? p ? = ? ? ? ? + + ? ? p p ? ? p ea o gm c = 2 bw (hz) vref v o r1 r3 c1 c2 r2 c o r o gm ea comp vsense type 2a type 2b type 1 c2 r3 c1 ea r2 a1 = gm ro| | r3 r1 + r2 ea aol(v/v) ro = gm ea r2 a0 = gm ro r1 + r2 1 p1 2 ro c1 = p a0a1 p1 z1 p2 aol bw
tps54260 slvsa86 ? march 2010 www.ti.com detailed description (continued) (24) (25) (26) (27) 28 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 1 z1 2 r3 c1 = p p o o 1 p2 = type 2b 2 r3 | | r c p o o 1 p2 = type 1 2 r (c2 + c ) p o o 1 p2 = type 2a 2 r3 | | r (c2 + c )
tps54260 www.ti.com slvsa86 ? march 2010 application information design guide ? step-by-step design procedure this example details the design of a high frequency switching regulator design using ceramic output capacitors. a few parameters must be known in order to start the design process. these parameters are typically determined at the system level. for this example, we will start with the following known parameters: output voltage 3.3 v transient response 0 to 1.5a load step vout = 3 % maximum output current 2.5 a input voltage 12 v nom. 10.8 v to 13.2 v output voltage ripple 1% of vout start input voltage (rising vin) 6.0 v stop input voltage (falling vin) 5.5 v selecting the switching frequency the first step is to decide on a switching frequency for the regulator. typically, the user will want to choose the highest switching frequency possible since this will produce the smallest solution size. the high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. the switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage and the output voltage and the frequency shift limitation. equation 12 and equation 13 must be used to find the maximum switching frequency for the regulator, choose the lower value of the two equations. switching frequencies higher than these values will result in pulse skipping or the lack of overcurrent protection during a short circuit. the typical minimum on time, t onmin , is 135 ns for the tps54260. for this example, the output voltage is 3.3 v and the maximum input voltage is 13.2 v, which allows for a maximum switch frequency up to 2247 khz when including the inductor resistance, on resistance output current and diode voltage in equation 12 . to ensure overcurrent runaway is not a concern during short circuits in your design use equation 13 or the solid curve in figure 40 to determine the maximum switching frequency. with a maximum input voltage of 13.2 v, assuming a diode voltage of 0.7 v, inductor resistance of 26 m ? , switch resistance of 200 m ? , a current limit value of 3.5 a and a short circuit output voltage of 0.2 v. the maximum switching frequency is approximately 4449 khz. for this design, a much lower switching frequency of 300 khz is used. to determine the timing resistance for a given switching frequency, use equation 11 or the curve in figure 39 . the switching frequency is set by resistor r 3 shown in figure 49 for 300 khz operation a 412 k resistor is required. copyright ? 2010, texas instruments incorporated submit documentation feedback 29 product folder link(s): tps54260
tps54260 slvsa86 ? march 2010 www.ti.com figure 49. 3.3v output tps54260 design example. output inductor selection (l o ) to calculate the minimum value of the output inductor, use equation 28 . k ind is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. the inductor ripple current will be filtered by the output capacitor. therefore, choosing high inductor ripple currents will impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. in general, the inductor ripple value is at the discretion of the designer; however, the following guidelines may be used. for designs using low esr output capacitors such as ceramics, a value as high as k ind = 0.3 may be used. when using higher esr output capacitors, k ind = 0.2 yields better results. since the inductor ripple current is part of the pwm control system, the inductor ripple current should always be greater than 150 ma for dependable operation. in a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side. this allows the inductor to still have a measurable ripple current with the input voltage at its minimum. for this design example, use k ind = 0.3 and the minimum inductor value is calculated to be 11 m h. for this design, a nearest standard value was chosen: 10 m h. for the output filter inductor, it is important that the rms current and saturation current ratings not be exceeded. the rms and peak inductor current can be found from equation 30 and equation 31 . for this design, the rms inductor current is 2.51 a and the peak inductor current is 2.913 a. the chosen inductor is a coilcraft mss1038-103nlb . it has a saturation current rating of 4.52 a and an rms current rating of 4.05 a. as the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. selecting higher ripple currents will increase the output voltage ripple of the regulator but allow for a lower inductance value. the current flowing through the inductor is the inductor ripple current plus the output current. during power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. in transient conditions, the inductor current can increase up to the switch current limit of the device. for this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. (28) 30 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 ind vinmax vout vout lo min = io k vinmax ?sw -
tps54260 www.ti.com slvsa86 ? march 2010 (29) (30) (31) output capacitor there are three primary considerations for selecting the value of the output capacitor. the output capacitor will determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in load current. the output capacitance needs to be selected based on the more stringent of these three criteria. the desired response to a large change in the load current is the first criteria. the output capacitor needs to supply the load with current when the regulator can not. this situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. the regulator also will temporarily not be able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. the regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. the output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. the output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. equation 32 shows the minimum output capacitance necessary to accomplish this. where iout is the change in output current, ? sw is the regulators switching frequency and vout is the allowable change in the output voltage. for this example, the transient load response is specified as a 3% change in vout for a load step from 1.5 a to 2.5 a (full load). for this example, iout = 2.5-1.5 = 1.0 a and vout = 0.03 3.3 = 0.099 v. using these numbers gives a minimum capacitance of 67 m f. this value does not take the esr of the output capacitor into account in the output voltage change. for ceramic capacitors, the esr is usually small enough to ignore in this calculation. aluminum electrolytic and tantalum capacitors have higher esr that should be taken into account. the catch diode of the regulator can not sink current so any stored energy in the inductor will produce an output voltage overshoot when the load current rapidly decreases, see figure 50 . the output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. the excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. the capacitor must be sized to maintain the desired output voltage during these transient periods. equation 33 is used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. where l is the value of the inductor, i oh is the output current under heavy load, i ol is the output under light load, vf is the final peak output voltage, and vi is the initial capacitor voltage. for this example, the worst case load step will be from 2.5 a to 1.5 a. the output voltage will increase during this load transition and the stated maximum in our specification is 3 % of the output voltage. this will make vf = 1.03 3.3 = 3.399. vi is the initial capacitor voltage which is the nominal output voltage of 3.3 v. using these numbers in equation 33 yields a minimum capacitance of 60 m f. equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification. where fsw is the switching frequency, v oripple is the maximum allowable output voltage ripple, and i ripple is the inductor ripple current. equation 34 yields 12 m f. equation 35 calculates the maximum esr an output capacitor can have to meet the output voltage ripple specification. equation 35 indicates the esr should be less than 36 m ? . the most stringent criteria for the output capacitor is 67 m f of capacitance to keep the output voltage in regulation during an load transient. additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase this minimum value. for this example, 2 x 47 m f, 10 v ceramic capacitors with 3 m ? of esr will be used. the derated capacitance is 72.4 f, above the minimum required capacitance of 67 f. copyright ? 2010, texas instruments incorporated submit documentation feedback 31 product folder link(s): tps54260 ( ) = f out out ripple o sw v vin max - v i vin max l ( ) ( ) 2 2 out out l(rms) o o sw v vinmax - v 1 i i 12 vinmax l ? ? = + ? ? ? f 2 iripple iout ilpeak + =
tps54260 slvsa86 ? march 2010 www.ti.com capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. an output capacitor that can support the inductor ripple current must be specified. some capacitor data sheets specify the root mean square (rms) value of the maximum ripple current. equation 36 can be used to calculate the rms ripple current the output capacitor needs to support. for this application, equation 36 yields 238 ma. (32) (33) (34) 32 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 1 1 oripple ripple cout > v 8 sw i | 2 iout cout > sw vout d | d ( ) ( ) 2 2 2 2 ioh iol cout > lo v vi - | -
tps54260 www.ti.com slvsa86 ? march 2010 (35) (36) catch diode the tps54260 requires an external catch diode between the ph pin and gnd. the selected diode must have a reverse voltage rating equal to or greater than vinmax. the peak current rating of the diode must be greater than the maximum inductor current. the diode should also have a low forward voltage. schottky diodes are typically a good choice for the catch diode due to their low forward voltage. the lower the forward voltage of the diode, the higher the efficiency of the regulator. typically, the higher the voltage and current ratings the diode has, the higher the forward voltage will be. although the design example has an input voltage up to 13.2v, a diode with a minimum of 60v reverse voltage is selected to allow input voltage transients up to the rated voltage of the tps54260. for the example design, the b360b-13-f schottky diode is selected for its lower forward voltage and it comes in a larger package size which has good thermal characteristics over small devices. the typical forward voltage of the b360b-13-f is 0.70 volts. the diode must also be selected with an appropriate power rating. the diode conducts the output current during the off-time of the internal power switch. the off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. the output current during the off-time is multiplied by the forward voltage of the diode which equals the conduction losses of the diode. at higher switch frequencies, the ac losses of the diode need to be taken into account. the ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery. equation 37 is used to calculate the total power dissipation, conduction losses plus ac losses, of the diode. the b360b-13-f has a junction capacitance of 200 pf. using equation 37 , the selected diode will dissipate 1.32 watts. if the power supply spends a significant amount of time at light load currents or in sleep mode consider using a diode which has a low leakage current and slightly higher forward voltage drop. (37) input capacitor the tps54260 requires a high quality ceramic, type x5r or x7r, input decoupling capacitor of at least 3 m f of effective capacitance and in some applications a bulk capacitance. the effective capacitance includes any dc bias effects. the voltage rating of the input capacitor must be greater than the maximum input voltage. the capacitor must also have a ripple current rating greater than the maximum input current ripple of the tps54260. the input ripple current can be calculated using equation 38 . the value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. the capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. x5r and x7r ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. the output capacitor must also be selected with the dc bias taken into account. the capacitance value of a capacitor decreases as the dc bias across a capacitor increases. for this example design, a ceramic capacitor with at least a 60v voltage rating is required to support the maximum input voltage. common standard ceramic capacitor voltage ratings include 4v, 6.3v, 10v, 16v, 25v, 50v or 100v so a 100v capacitor should be selected. for this example, two 2.2 m f, 100v capacitors in parallel have been selected. table 2 shows a selection of high voltage capacitors. the input capacitance value determines the input ripple voltage of the regulator. the input voltage ripple can be calculated using equation 39 . using the design example values, ioutmax = 2.5 a, cin = 4.4 m f, ? sw = 300 khz, yields an input voltage ripple of 206 mv and a rms input ripple current of 1.15 a. copyright ? 2010, texas instruments incorporated submit documentation feedback 33 product folder link(s): tps54260 vout (vin max vout) icorms = 12 vin max lo sw - | oripple esr ripple v r i < ( ) 2 - cj ?sw vin + v?d (vin max vout) iout v?d pd = + 2 vin max
tps54260 slvsa86 ? march 2010 www.ti.com (38) (39) table 2. capacitor types vendor value ( m f) eia size voltage dialectric comments 1.0 to 2.2 100 v 1210 grm32 series 1.0 to 4.7 50 v murata 1.0 100 v 1206 grm31 series 1.0 to 2.2 50 v 1.0 10 1.8 50 v 2220 1.0 to 1.2 100 v vishay vj x7r series 1.0 to 3.9 50 v 2225 1.0 to 1.8 100 v x7r 1.0 to 2.2 100 v 1812 c series c4532 1.5 to 6.8 50 v tdk 1.0. to 2.2 100 v 1210 c series c3225 1.0 to 3.3 50 v 1.0 to 4.7 50 v 1210 1.0 100 v avx x7r dielectric series 1.0 to 4.7 50 v 1812 1.0 to 2.2 100 v slow start capacitor the slow start capacitor determines the minimum amount of time it will take for the output voltage to reach its nominal programmed value during power up. this is useful if a load requires a controlled voltage slew rate. this is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. the large currents necessary to charge the capacitor may make the tps54260 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. limiting the output voltage slew rate solves both of these problems. the slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. equation 40 can be used to find the minimum slow start time, tss, necessary to charge the output capacitor, cout, from 10% to 90% of the output voltage, vout, with an average slow start current of issavg. in the example, to charge the effective output capacitance of 72.4 f up to 3.3v while only allowing the average output current to be 1 a would require a 0.19 ms slow start time. once the slow start time is known, the slow start capacitor value can be calculated using equation 6 . for the example circuit, the slow start time is not too critical since the output capacitor value is 2 x 47 m f which does not require much current to charge to 3.3v. the example circuit has the slow start time set to an arbitrary value of 3.5 ms which requires a 8.75 nf slow start capacitor. for this design, the next larger standard value of 10 nf is used. (40) bootstrap capacitor selection a 0.1- m f ceramic capacitor must be connected between the boot and ph pins for proper operation. it is recommended to use a ceramic capacitor with x5r or better grade dielectric. the capacitor should have a 10v or higher voltage rating. 34 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 iout max 0.25 vin = cin sw | ( ) vin min vout vout icirms = iout vin min vin min - cout vout 0.8 tss > issavg
tps54260 www.ti.com slvsa86 ? march 2010 under voltage lock out set point the under voltage lock out (uvlo) can be adjusted using an external voltage divider on the en pin of the tps54260. the uvlo has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. for the example design, the supply should turn on and start switching once the input voltage increases above 6.0 v (enabled). after the regulator starts switching, it should continue to do so until the input voltage falls below 5.5 v (uvlo stop). the programmable uvlo and enable voltages are set using the resistor divider of r1 and r2 between vin and ground to the en pin. equation 2 through equation 3 can be used to calculate the resistance values necessary. for the example application, a 124 k ? between vin and en (r1) and a 30.1 k ? between en and ground (r2) are required to produce the 6.0 and 5.5 volt start and stop voltages. output voltage and feedback resistors selection the voltage divider of r5 and r6 is used to set the output voltage. for the example design, 10.0 k ? was selected for r6. using equation 1 , r5 is calculated as 31.25 k ? . the nearest standard 1% resistor is 31.6 k ? . due to current leakage of the vsense pin, the current flowing through the feedback network should be greater than 1 m a in order to maintain the output voltage accuracy. this requirement makes the maximum value of r2 equal to 800 k ? . choosing higher resistor values will decrease quiescent current and improve efficiency at low output currents but may introduce noise immunity problems. compensation there are several methods used to compensate dc/dc regulators. the method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. since the slope compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency used in the calculations. this method assumes the crossover frequency is between the modulator pole and the esr zero and the esr zero is at least 10 times greater the modulator pole. use switcherpro software for a more accurate design. to get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using equation 41 and equation 42 . for cout, use a derated value of 40 m f. use equations equation 43 and equation 44 , to estimate a starting point for the crossover frequency, fco, to design the compensation. for the example design, fpmod is 1206 hz and fzmod is 530.5 khz. equation 43 is the geometric mean of the modulator pole and the esr zero and equation 44 is the mean of modulator pole and the switching frequency. equation 43 yields 25.3 khz and equation 44 gives 13.4 khz. use the lower value of equation 43 or equation 44 for an initial crossover frequency. for this example, a higher fco is desired to improve transient response. the target fco is 35.0 khz. next, the compensation components are calculated. a resistor in series with a capacitor is used to create a compensating zero. a capacitor in parallel to these two components forms the compensating pole. (41) (42) (43) (44) to determine the compensation resistor, r4, use equation 45 . assume the power stage transconductance, gmps, is 10.5a/v. the output voltage, vo, reference voltage, vref, and amplifier transconductance, gmea, are 3.3v, 0.8v and 310 m a/v, respectively. r4 is calculated to be 20.2 k ? , use the nearest standard value of 20.0 k ? . use equation 46 to set the compensation zero to the modulator pole frequency. equation 46 yields 4740 pf for compensating capacitor c5, a 4700 pf is used for this design. (45) copyright ? 2010, texas instruments incorporated submit documentation feedback 35 product folder link(s): tps54260 ioutmax p mod = 2 vout cout | p p z f f f = co mod mod 2 f gmps gmea p ? ? ? ? = ? ? ? ? co out out ref c v r4 v 1 z mod = 2 resr cout | p 2 sw p f f f = co mod
tps54260 slvsa86 ? march 2010 www.ti.com (46) a compensation pole can be implemented if desired using an additional capacitor c8 in parallel with the series combination of r4 and c5. use the larger value of equation 47 and equation 48 to calculate the c8, to set the compensation pole. c8 is not used for this design example. (47) (48) discontinuous mode and eco mode boundary with an input voltage of 12 v, the power supply enters discontinuous mode when the output current is less than 337 ma. the power supply enters ecomode when the output current is lower than 5 ma. the input current draw at no load is 392 m a. application curves figure 50. load transient figure 51. startup with vin figure 52. output ripple ccm figure 53. output ripple, dcm 36 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 1 sw f p = c8 r4 vout = 20 mv / div (ac coupled) ph = 5 v / div time = 2 usec / div re = o c sr c8 r4 vout = 50 mv / div (ac coupled) output current = 1 a / div (load step 1.5 a to 2.5 a) time = 200 usec / div vout = 20 mv / div (ac coupled) ph = 5 v / div time = 2 usec / div vin = 10 v / div vout = 2 v / div en = 2 v / div ss/tr = 2 v / div time = 5 msec / div p 1 c5 2 r4 mod = f p
tps54260 www.ti.com slvsa86 ? march 2010 figure 54. output ripple, psm figure 55. input ripple ccm figure 56. input ripple dcm figure 57. efficiency vs load current figure 58. light load efficiency figure 59. overall loop frequency response copyright ? 2010, texas instruments incorporated submit documentation feedback 37 product folder link(s): tps54260 vout = 20 mv / div (ac coupled) ph = 5 v / div time = 10 usec / div 0 10 20 30 40 50 60 70 80 100 0.001 0.01 i - output current - a o efficiency - % 0.1 90 vin=12vvout=3.3v fsw=300khz 0 10 20 30 40 50 60 70 80 100 0 0.5 1.0 1.5 2.0 i - output current - a o efficiency - % 2.5 3.0 90 vin=12vvout=3.3v fsw=300khz vin = 200 mv / div (ac coupled) ph = 5 v / div time = 2 usec / div vin = 50 mv / div (ac coupled) ph = 5 v / div time = 2 usec / div 10 1-10 3 -60 -40 0 20 40 60 -180 -120 -60 0 60 120 180 f - frequency - hz gain - db phase - o 1-10 4 1-10 5 1-10 6 -20 100 gain phase vin=12 vvout=3.3v iout=2.5a
tps54260 slvsa86 ? march 2010 www.ti.com figure 60. regulation vs load current figure 61. regulation vs input voltage 38 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 3.3 3.32 3.34 3.36 3.38 3.4 10.8 12 i - output current - a o v - o output voltage - v 13.2 vin=12vvout=3.3v fsw=300khz iout=1.5a 11.6 11.2 12.8 12.4 3.3 3.32 3.34 3.36 3.38 3.4 0 1.5 i - output current - a o v - o o utput voltage - v 3.0 vin=12vvout=3.3v fsw=300khz 1.0 0.5 2.5 2.0
tps54260 www.ti.com slvsa86 ? march 2010 power dissipation estimate the following formulas show how to estimate the ic power dissipation under continuous conduction mode (ccm) operation. these equations should not be used if the device is working in discontinuous conduction mode (dcm). the power dissipation of the ic includes conduction loss (pcon), switching loss (psw), gate drive loss (pgd) and supply current (pq). (49) (50) (51) (52) where: iout is the output current (a). r ds(on) is the on-resistance of the high-side mosfet ( ? ). vout is the output voltage (v). vin is the input voltage (v). fsw is the switching frequency (hz). so (53) for given t a , (54) for given t jmax = 150 c (55) where: ptot is the total device power dissipation (w). t a is the ambient temperature ( c). t j is the junction temperature ( c). rth is the thermal resistance of the package ( c/w). t jmax is maximum junction temperature ( c). t amax is maximum ambient temperature ( c). there will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and trace resistance that will impact the overall efficiency of the regulator. copyright ? 2010, texas instruments incorporated submit documentation feedback 39 product folder link(s): tps54260 2 ds(on) vout pcon = io r vin 6 pq = 116 10 vin - 2 9 psw = vin sw lo 0.25 10 - | tamax = tjmax rth ptot - 9 pgd = vin 3 10 sw - | tj = ta + rth ptot ptot = pcon + psw + pgd + pq
tps54260 slvsa86 ? march 2010 www.ti.com layout layout is a critical portion of good power supply design. there are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. to help eliminate these problems, the vin pin should be bypassed to ground with a low esr ceramic bypass capacitor with x5r or x7r dielectric. care should be taken to minimize the loop area formed by the bypass capacitor connections, the vin pin, and the anode of the catch diode. see figure 62 for a pcb layout example. the gnd pin should be tied directly to the power pad under the ic and the power pad. the power pad should be connected to any internal pcb ground planes using multiple vias directly under the ic. the ph pin should be routed to the cathode of the catch diode and to the output inductor. since the ph connection is the switching node, the catch diode and output inductor should be located close to the ph pins, and the area of the pcb conductor minimized to prevent excessive capacitive coupling. for operation at full rated load, the top side ground area must provide adequate heat dissipating area. the rt/clk pin is sensitive to noise so the rt resistor should be located as close as possible to the ic and routed with minimal lengths of trace. the additional external components can be placed approximately as shown. it may be possible to obtain acceptable performance with alternate pcb layouts, however this layout has been shown to produce good results and is meant as a guideline. figure 62. pcb layout example estimated circuit area the estimated printed circuit board area for the components used in the design of figure 49 is 0.55 in 2 . this area does not include test points or connectors. 40 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260 bootvin en ss/tr rt/clk ph gnd comp vsense pwrgd inputbypass capacitor uvloadjust resistors slow startcapacitor frequencyset resistor compensationnetwork resistordivider outputinductor output capacitor vout vin topside ground area catchdiode route boot capacitor trace on another layer to provide wide path for topside ground thermal via signal via
tps54260 www.ti.com slvsa86 ? march 2010 figure 63. tps54260 inverting power supply from slva317 application note figure 64. tps54260 split rail power supply based on slva369 application note copyright ? 2010, texas instruments incorporated submit documentation feedback 41 product folder link(s): tps54260 ph vin gnd boot vsense comp tps54260 en rt/clk ss/tr cpole czero rcomp rt css coneg lo cboot cin r1 r2 cd vin voneg + + gnd vopos copos + ph vin gnd boot vsense comp tps54260 en rt/clk ss/tr cpole czero rcomp rt css co lo cboot cin r1 r2 cd vin vout + + gnd
tps54260 slvsa86 ? march 2010 www.ti.com figure 65. 12v to 3.8v gsm power supply figure 66. 24v to 4.2v gsm power supply 42 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps54260
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) TPS54260DGQ active msop- power pad dgq 10 80 green (rohs & no sb/br) cu nipdau level-1-260c-unlim TPS54260DGQr active msop- power pad dgq 10 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 29-mar-2010 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS54260DGQr msop- power pad dgq 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 q1 package materials information www.ti.com 20-jul-2010 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS54260DGQr msop-powerpad dgq 10 2500 346.0 346.0 35.0 package materials information www.ti.com 20-jul-2010 pack materials-page 2

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